A Verification Environment for an Embedded Processor By Nick Heaton and Ed Flaherty Tough verification challenges may be manageable after all.

What is Full Custom Layout Design? By Dan Clein The categories, flows, and tools often need definition and clarification. Driving a 32-Bit RISC Processor in an FPGA By Yanzhe Liu and Greg Kahlert -Sidebar by Grant Dearden Achieving ASIC-like clock speeds in an FPGA is hard work. Functionality Support in HDLs By Larry Saunders and Yuri Tatarnikov A simple bi-directional pass gate can present surprising complexities. Re-engineering the Art of Timing Sign-Off By John Croix New modeling approaches deliver accurate timing sign-off at 0.15 µm. Focus Report: Power and Timing By Peggy Aycinena

DAC to the Future By Steven E.Schulz Phil Kaufman Award By Peggy Aycinena

Tech Bits By William Dowell Hardware Considerations for Information Appliance Design

Editorial By Ron Wilson A New DAC and a Starkly New World Viewpoint By Jan Rabaey Verification at DAC 2001

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